3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)

Press/Media

Period	2024.09.12

Media coverage

Title	3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
Media name/outlet	Semiconductor Engineering
Country/Territory	United States
Date	24.09.12
URL	https://semiengineering.com/3d-ic-partitioning-and-placement-method-that-optimizes-for-critical-paths-postech/
Persons	Min Jae Kim