1.6Gb/s clock and data recovery circuit of oversampling method without the reference clock

In this paper, an 1.6Gb/s clock and data recovery(CDR) circuit for a high-speed serial link without the reference clock is described. It has a phase and frequency detector (PD and FD), which incorporates a half-rate bang-bang type oversampling PD and a half-rate digital quadricorrelator frequency detector (DQFD) that can achieve low-jitter operation and improve pull-in range. The PD of oversamping method finds a phase error by generating four phase up/down signals. The FD of quadricorrelator method finds a frequency error by generating frequency up/down signals. Therefore these six signals control three charge pump respectively. It also has a ring oscillator type voltage controlled oscillator (VCO) and three charge pumps (CP). The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the VCO tuning range and tuning linearity. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process. The designed circuit consumes 130mW from 1.8V supply voltage according to simulation results.