Abstract
A 1.9-GHz single-stage differential stacked-FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32-μm 2.8-V thick-oxide MOSFETs in a 0.18-μm silicon-on-insulator CMOS process. The input cross-coupled stacked-FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked-FET power amplifier in sub-micrometer CMOS technology. With a 4-V supply voltage, the proposed power amplifier with an integrated output coupled-resonator balun showed a small-signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power-added efficiency of 41.5% at the operating frequency.
| Original language | English |
|---|---|
| Pages (from-to) | 1660-1672 |
| Number of pages | 13 |
| Journal | International Journal of Circuit Theory and Applications |
| Volume | 45 |
| Issue number | 11 |
| DOIs | |
| State | Published - 2017.11 |
Keywords
- breakdown
- cascode
- CMOS
- cross-coupled
- front-end module
- power-added efficiency
- saturated output power
- silicon-on-insulator
- stacked-FET
Quacquarelli Symonds(QS) Subject Topics
- Materials Science
- Computer Science & Information Systems
- Mathematics
- Engineering - Electrical & Electronic
- Engineering - Petroleum
- Data Science
Fingerprint
Dive into the research topics of 'A 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier with uniformly distributed voltage stresses'. Together they form a unique fingerprint.Cite this
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver