@inproceedings{9a253f97b84248e58019d22d4d9fbcd9,
title = "A Current-link CMOS Analog Neuron with Simplified Synapse Using a Merged Switch Array",
abstract = "A new current-mode analog neuron with a current link between the soma and the synapse is proposed. The proposed neuron requires fewer number of transistors for its synapse due to the merged switch array used for binary weighting. Thus, the burden of hardware complexity for the current-link current-mode neuron is significantly alleviated. The proposed neuron and SRAM cells for weight storage were designed in 0.18μm CMOS process for verification purposes. The simulated linearity of the neuron is sufficiently good to do without calibration of each neuron. Test chips are under fabrication.",
keywords = "Analog Neurons, CMOS, Current-mode",
author = "Yang, \{Hee Yeon\} and Noh, \{Yu Jin\} and Lee, \{Sung Ho\} and Kim, \{Geun Won\} and Jeong, \{Hang Geun\} and Donggu Im",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",
year = "2020",
month = oct,
day = "21",
doi = "10.1109/ISOCC50952.2020.9332923",
language = "English",
series = "Proceedings - International SoC Design Conference, ISOCC 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "77--78",
booktitle = "Proceedings - International SoC Design Conference, ISOCC 2020",
}