A Fully Integrated High Efficiency RF Power Amplifier for WLAN Application in 40 nm Standard CMOS Process

This paper proposes a CMOS linear power amplifier (PA) design scheme for IEEE 802.11g (WLAN) application. The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. Based on the un-even bias scheme, the power stage can improve linearity and reduce current consumption in the low power region. It is fabricated with a TSMC 40 nm standard RF CMOS process. The measurements show that the designed PA reaches a 1 dB gain compression output power of 24.6 dBm and a peak drain efficiency of 38% with a 3.3 V power supply at 2.4 GHz operating frequency range. When the PA was tested with an IEEE 802.11g OFDM signal of 20 MHz channel bandwidth, the obtained -25 dB EVM compliant output power and drain efficiency are 18.5 dBm and 14%, respectively.