A high IIP2 broadband CMOS low-noise amplifier with a dual-loop feedback

A dual-loop feedback broadband low-noise amplifier (LNA) employing second-order inter-modulation distortion (IMD2) cancellation is implemented in an 0.18- μm silicon-on-insulator (SOI) CMOS technology. The dual-loop feedback configuration stabilizes an input return loss (S₁₁) of the LNA at the VHF low band around 50 MHz with small dc blocking capacitors. In order to achieve a second-order output-referred intercept point (OIP2) of greater than +50 dBm with reasonably low power consumption, all of the building blocks of the proposed LNA are designed to have a complementary configuration while the body-bias control technique is applied to the inverter-based resistive feedback amplifier. In addition, the peaking inductor is placed inside the feedback loop at the gate of the input transistor to enhance the bandwidth of the LNA. The designed LNA achieves a measured power gain ( S -{21} ) of 10.1 dB, a noise figure (NF) of less than 4 dB, and an input return loss ( S -{11} ) of greater than 10 dB over frequencies ranging from 50 MHz to 3 GHz. The measurements show a third-order output-referred intercept point (OIP3) of +17.8 dBm and an OIP2 of +53 dBm at 1 GHz.