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A low noise amplifier simultaneously achieving input impedance and minimum noise matching

  • Bum Kyum Kim*
  • , Donggu Im
  • , Jaeyoung Choi
  • , Kwyro Lee
  • *Corresponding author for this work
  • Korea Advanced Institute of Science and Technology

Research output: Contribution to conferenceConference paperpeer-review

Abstract

A CMOS complementary capacitive loaded LNA with inductively source degeneration is implemented for 900MHz application using a 0.18-μm CMOS process. In order to achieve simultaneous input impedance and minimum noise matching, the capacitive loading technique is proposed. Owing to the capacitive loading technique, the noise figure (NF) of the proposed LNA can be perfectly close to NFmin while maintaining the source impedance matching by reducing the source degeneration inductor and gate inductor contrast to conventional cascode LNA with inductively source degeneration. The measurements demonstrate that the LNA has a power gain of 12 dB, a NF of 1 dB, an IIP3 of +7.7 dBm, and an input P1-dB of -5 dBm at 900 MHz while drawing 9 mA from a 1.8 V supply voltage.

Original languageEnglish
Title of host publication2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Digest of Papers
DOIs
StatePublished - 2011
Event2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011 - Baltimore, MD, United States
Duration: 2011.06.52011.06.7

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2011 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2011
Country/TerritoryUnited States
CityBaltimore, MD
Period11.06.511.06.7

Keywords

  • capacitive load
  • complementary
  • input impedance matching
  • low noise amplifier
  • noise matching
  • simultaneous matching

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