A modified CMOS frequency doubler considering delay time matching condition

  • Sujin Seo*
  • , Yongchae Jeong
  • , J. Stevenson Kenney
  • *Corresponding author for this work

Research output: Contribution to conferenceConference paperpeer-review

Abstract

In this paper, a frequency doubler is designed that converts from 1.15GHz input signal to 2.3 GHz output signal using TSMC 0.18 CMOS Technology. The proposed doubler consist of a fully adjustable Schmitt trigger (FAST), time-delay components, XOR gate and a voltage controlled delay line (VCDL). Time-delay components use RC integrator and comparator. Advantages of this topology include good fundamental frequency and harmonic frequency suppression, compact layout and low power consumption. The desired signal at 2.3 GHz is 0.871 dBm. The fundamental frequency at 1.15 GHz and third harmonic frequency at 3.45 GHz approximately 37 dBc below the 2.3 GHz signal. The fourth harmonic frequency at 4.6 GHz is approximately 24 dBc below the 2.3 GHz signal. The power consumption is 11.07 m W and the phase noise of the output signal is 100.5 dBc/Hz at 10 KHz offset.

Original languageEnglish
Title of host publicationProceedings - 2007 International Symposium on Information Technology Convergence, ISITC 2007
Pages392-395
Number of pages4
DOIs
StatePublished - 2007
Event2007 International Symposium on Information Technology Convergence, ISITC 2007 - Jeonju, Korea, Republic of
Duration: 2007.11.232007.11.24

Publication series

NameProceedings - 2007 International Symposium on Information Technology Convergence, ISITC 2007

Conference

Conference2007 International Symposium on Information Technology Convergence, ISITC 2007
Country/TerritoryKorea, Republic of
CityJeonju
Period07.11.2307.11.24

Quacquarelli Symonds(QS) Subject Topics

  • Computer Science & Information Systems
  • Communication & Media Studies

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