A novel capacitorless DRAM cell using superlattice bandgap-engineered (SBE) structure with 30-nm channel length

Sunyeong Lee; Ja Sun Shin; Jaeman Jang; Hagyoul Bae; Daeyoun Yun; Jieun Lee; Dae Hwan Kim; Dong Myong Kim

doi:10.1109/TNANO.2010.2098885

A novel capacitorless DRAM cell using superlattice bandgap-engineered (SBE) structure with 30-nm channel length

Sunyeong Lee^*
, Ja Sun Shin
, Jaeman Jang
, Hagyoul Bae
, Daeyoun Yun
, Jieun Lee
, Dae Hwan Kim
, Dong Myong Kim

^*Corresponding author for this work

Division of Electronic Engineering

Kookmin University

Research output: Contribution to journal › Journal article › peer-review

13 Scopus citations

Abstract

We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F² feature size. Thanks to the Si_0.8Ge_0.2 superlattice quantum well and silicon dioxide (SiO₂) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10ms for the retention time.

Original language	English
Article number	5667061
Pages (from-to)	1023-1030
Number of pages	8
Journal	IEEE Transactions on Nanotechnology
Volume	10
Issue number	5
DOIs	https://doi.org/10.1109/TNANO.2010.2098885
State	Published - 2011.09

Keywords

2-D TCAD
capacitorless dynamic random access memory (DRAM)
retention
sensing margin
silicon dioxide (SiO) physical barrier
superlattice

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10.1109/TNANO.2010.2098885

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title = "A novel capacitorless DRAM cell using superlattice bandgap-engineered (SBE) structure with 30-nm channel length",

abstract = "We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F2 feature size. Thanks to the Si0.8Ge0.2 superlattice quantum well and silicon dioxide (SiO2) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10ms for the retention time.",

keywords = "2-D TCAD, capacitorless dynamic random access memory (DRAM), retention, sensing margin, silicon dioxide (SiO) physical barrier, superlattice",

author = "Sunyeong Lee and Shin, \{Ja Sun\} and Jaeman Jang and Hagyoul Bae and Daeyoun Yun and Jieun Lee and Kim, \{Dae Hwan\} and Kim, \{Dong Myong\}",

year = "2011",

month = sep,

doi = "10.1109/TNANO.2010.2098885",

language = "English",

volume = "10",

pages = "1023--1030",

journal = "IEEE Transactions on Nanotechnology",

issn = "1536-125X",

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AU - Lee, Sunyeong

AU - Shin, Ja Sun

AU - Jang, Jaeman

AU - Bae, Hagyoul

AU - Yun, Daeyoun

AU - Lee, Jieun

AU - Kim, Dae Hwan

AU - Kim, Dong Myong

PY - 2011/9

Y1 - 2011/9

N2 - We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F2 feature size. Thanks to the Si0.8Ge0.2 superlattice quantum well and silicon dioxide (SiO2) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10ms for the retention time.

AB - We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F2 feature size. Thanks to the Si0.8Ge0.2 superlattice quantum well and silicon dioxide (SiO2) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10ms for the retention time.

KW - 2-D TCAD

KW - capacitorless dynamic random access memory (DRAM)

KW - retention

KW - sensing margin

KW - silicon dioxide (SiO) physical barrier

KW - superlattice

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U2 - 10.1109/TNANO.2010.2098885

DO - 10.1109/TNANO.2010.2098885

M3 - Journal article

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EP - 1030

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JF - IEEE Transactions on Nanotechnology

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ER -

A novel capacitorless DRAM cell using superlattice bandgap-engineered (SBE) structure with 30-nm channel length

Abstract

Keywords

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