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A Novel Multiplexer-Based Low-Power Full Adder

  • Yingtao Jiang
  • , Abdulkarim Al-Sheraidah
  • , Yuke Wang
  • , Edwin Sha
  • , Jin Gyun Chung
  • University of Nevada, Las Vegas
  • University of Texas at Dallas

Research output: Contribution to journalJournal articlepeer-review

Abstract

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Original languageEnglish
Pages (from-to)345-348
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume51
Issue number7
DOIs
StatePublished - 2004.07

Keywords

  • Full adder
  • low power
  • multiplexer
  • very large-scale integrated (VLSI) circuit

Quacquarelli Symonds(QS) Subject Topics

  • Engineering - Electrical & Electronic
  • Engineering - Petroleum

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