A RF PVT compensated negative resistance circuit for Q-factor improvement of passive elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolute-temperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Q-factor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 GHz under typical corner conditions (tt, 1.2V, 27 °C). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.