A Sub-GHz Wideband CMOS Receiver Front-End With 49 dB Gain Range and Constant OIP3 Across Gain Reduction

This work presents a sub-GHz (400 MHz ∼ 950 MHz) wideband CMOS receiver front-end with a 49 dB gain range and constant output-referred third-order intercept point (OIP3) across gain reduction, implemented in a 130-nm CMOS process for IoT applications. To enhance loop gain and improve the noise figure (NF) while achieving wideband input impedance matching, the differential outputs from the single-to-differential (S2D) converter are converted into a single-ended signal using a voltage-subtractor-based differential-to-single (D2S) buffer. This single-ended signal is then fed back to the input of the S2D converter through a feedback resistor. Additionally, two separate gain paths are implemented by employing two optimized S2D converters, one designed for low noise and the other for high linearity, to enable gain control while maintaining a nearly constant output 1 dB compression point (OP1dB) and OIP3. In particular, when very strong signals are received, the feedback path is disabled, and a pi-attenuator is activated in front of the S2D converter optimized for high linearity, in order to attenuate the signal while keeping a constant input impedance. A currentmode passive mixer with a transimpedance amplifier (TIA) is adopted to maintain low impedance and reduce the voltage swing at the mixer output, thereby enhancing linearity. In the measurement, the proposed receiver front-end shows an average conversion gain of 50.5 dB, NF of 3.3 dB, and OIP3 of + 24.3 dBm at high gain mode over the operating frequency band. In addition, it achieves a gain range of 49 dB with nearly constant OIP3. The current consumption is 12.4 mA from a 1.2 V supply.