Address code generation based on combined offset assignment and modify register optimization for digital signal processors

  • Gang Hee Yu*
  • , Dong Hyun Kim
  • , Jong Yeol Lee
  • *Corresponding author for this work

Research output: Contribution to conferenceConference paperpeer-review

Abstract

Exploitation of address generation units (AGUs) which are typically provided by digital signal processors (DSPs) plays an important role in DSP code generation. In this paper we propose an effective address code generation approach for DSPs to minimize the number of addressing instructions. Our work tightly couples general offset assignment (GOA) with modify register optimization (MRO) in an iterative framework. Experimental results with benchmarks show average improvements of 29% in the addressing cost over previous approaches.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Embedded Systems and Applications, ESA 2008
Pages284-288
Number of pages5
StatePublished - 2008
Event2008 International Conference on Embedded Systems and Applications, ESA 2008 - Las Vegas, NV, United States
Duration: 2008.07.142008.07.17

Publication series

NameProceedings of the 2008 International Conference on Embedded Systems and Applications, ESA 2008

Conference

Conference2008 International Conference on Embedded Systems and Applications, ESA 2008
Country/TerritoryUnited States
CityLas Vegas, NV
Period08.07.1408.07.17

Keywords

  • Compiler
  • DSP

Quacquarelli Symonds(QS) Subject Topics

  • Computer Science & Information Systems
  • Data Science

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