An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

Kyeong Sik Min; Young Hee Kim; Daejeong Kim; Dong Myeong Kim; Seong Ik Cho; Jin Hong Ahn; Jin Yong Chung

doi:10.1016/j.cap.2003.09.004

An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

Kyeong Sik Min^*
, Young Hee Kim
, Daejeong Kim
, Dong Myeong Kim
, Seong Ik Cho
, Jin Hong Ahn
, Jin Yong Chung

^*Corresponding author for this work

Division of Electronic Engineering

Kookmin University
Changwon National University
SK Corporation

Research output: Contribution to journal › Journal article › peer-review

1 Scopus citations

Abstract

A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-V_CC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.

Original language	English
Pages (from-to)	507-510
Number of pages	4
Journal	Current Applied Physics
Volume	3
Issue number	6
DOIs	https://doi.org/10.1016/j.cap.2003.09.004
State	Published - 2003.12

Keywords

Large-current-output charge pump
Low-voltage charge pump
Low-voltage circuit
Low-voltage DRAM circuit
Low-voltage generator
Low-voltage memory circuit
Negative word line

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10.1016/j.cap.2003.09.004

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@article{4fce60b9e6354164857d5e19d327cc46,

title = "An 80\% larger-current-output negative CMOS charge pump with 10\% area penalty for sub-1-V-VCC negative-word-line DRAMs",

abstract = "A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80\% larger than the conventional pump with the sacrificial 10\% area penalty. This new pump is regarded to be suitable to sub-1-V-VCC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.",

keywords = "Large-current-output charge pump, Low-voltage charge pump, Low-voltage circuit, Low-voltage DRAM circuit, Low-voltage generator, Low-voltage memory circuit, Negative word line",

author = "Min, \{Kyeong Sik\} and Kim, \{Young Hee\} and Daejeong Kim and Kim, \{Dong Myeong\} and Cho, \{Seong Ik\} and Ahn, \{Jin Hong\} and Chung, \{Jin Yong\}",

year = "2003",

month = dec,

doi = "10.1016/j.cap.2003.09.004",

language = "English",

volume = "3",

pages = "507--510",

journal = "Current Applied Physics",

issn = "1567-1739",

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T1 - An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

AU - Min, Kyeong Sik

AU - Kim, Young Hee

AU - Kim, Daejeong

AU - Kim, Dong Myeong

AU - Cho, Seong Ik

AU - Ahn, Jin Hong

AU - Chung, Jin Yong

PY - 2003/12

Y1 - 2003/12

N2 - A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-VCC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.

AB - A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-VCC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.

KW - Large-current-output charge pump

KW - Low-voltage charge pump

KW - Low-voltage circuit

KW - Low-voltage DRAM circuit

KW - Low-voltage generator

KW - Low-voltage memory circuit

KW - Negative word line

UR - https://www.scopus.com/pages/publications/0242635996

U2 - 10.1016/j.cap.2003.09.004

DO - 10.1016/j.cap.2003.09.004

M3 - Journal article

AN - SCOPUS:0242635996

SN - 1567-1739

VL - 3

SP - 507

EP - 510

JO - Current Applied Physics

JF - Current Applied Physics

IS - 6

ER -

An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-VCC negative-word-line DRAMs

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Keywords

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