An area-efficient merged synchronous mirror delay for delay locked loop and duty cycle correction

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. An SMD(Synchronous Mirror Delay) structure is used both for skew reduction and for DCC(Duty Cycle Correction). In this paper, an area-efficient DLL structure based on the merged dual SMD is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, yielding a 25% saving in the number of the required delay cells. The designed chip was fabricated using a 0.25-μm one-poly, four-metal CMOS process. Measurement of the fabricated chip showed that the acceptable duty-cycle of the input signal ranges from 80% to 20% when the clock frequency ranges from 400MHz to 600MHz. The locking and duty correction requires only 5 clock cycles with the corrected duty-cycle varying from 53% to 47%.