An effective interfacing adapter for PRAM based main memory via flexible management DRAM buffer

An interfacing adapter is required between cache layer and PRAM based main memory to cover the shortcomings of PRAM. Thus this research is to design a flexible DRAM buffer (FDB) structure, which can improves performance by prefetch candidate data into FDB to reduce the miss penalty, and extends PRAM lifetime by filtering a large portion of write back data upon eviction from last level cache. Our results show that FDB can effectively minimize the access latency to achieve similar performance to the case of DRAM main memory and reduce a certain degree of write count to PRAM, thus limited endurance can get some respite thereby, typically extend their life expectancy.