Characterization and Optimization of Inverted-T FinFET under Nanoscale Dimensions

In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current (I D) under the same dimension as that of a silicon-on-insulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width ( W fin), UTB height (H UTB), and gate length ( L g) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanical models. W fin below 10 nm is evaluated to be suitable for strong gate controllability. We first examine a critical H UTB, beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When H UTB = 3 and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled L g, although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times.