Abstract
Power handling capability is the most stringent specification for an RF switch. The dominant reason to limit the power handling capability is undesirable channel formation (leakage current) on off-state FEETs in the event of large signal input. To characterize leakage current and find the correlation between DC I-V measurement and RF P1 dB measurement, a new DC characterization method (Float FET I-V characterization method) reflecting RF switch operation is proposed. Based on the proposed Float FET I-V method, an experimental study on optimum dc bias point, MOSFET device design, and stacked-FETs device design is performed in order to achieve maximum power handling capability of the RF switch. In addition, compared to RF measurement tests that take a long time, the proposed characterization method rapidly evaluates the various off-state MOSFET leakage current mechanisms affecting the power handling capability of the RF switch.
| Original language | English |
|---|---|
| Pages (from-to) | 94-98 |
| Number of pages | 5 |
| Journal | Solid-State Electronics |
| Volume | 90 |
| DOIs | |
| State | Published - 2013 |
Keywords
- Gate induced drain leakage (GIDL)
- Power handling capability
- RF switch
- Silicon-on-Insulator (SOI) CMOS
- Source-drain punch through
- Stacked transistors
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