CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin

Seong Ik Cho; Jin Seok Heo; Hong June Park; Mu Hun Park; Young Hee Kim

CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin

Seong Ik Cho
, Jin Seok Heo
, Hong June Park
, Mu Hun Park
, Young Hee Kim

Division of Electronic Engineering

SK Corporation
Changwon National University
Pohang University of Science and Technology

Research output: Contribution to journal › Journal article › peer-review

3 Scopus citations

Abstract

A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.

Original language	English
Pages (from-to)	2508-2510
Number of pages	3
Journal	IEICE Transactions on Electronics
Volume	E86-C
Issue number	12
State	Published - 2003.12

Keywords

Flip-flop
Receiver
Sense-amplifier

Cite this

@article{4e37c1e8dbc84f05b2e0ca01b05e436d,

title = "CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin",

abstract = "A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22\%, the input data to clock skew by 46\% and the clock to output delay by 4.4\%.",

keywords = "Flip-flop, Receiver, Sense-amplifier",

author = "Cho, \{Seong Ik\} and Heo, \{Jin Seok\} and Park, \{Hong June\} and Park, \{Mu Hun\} and Kim, \{Young Hee\}",

year = "2003",

month = dec,

language = "English",

volume = "E86-C",

pages = "2508--2510",

journal = "IEICE Transactions on Electronics",

issn = "0916-8524",

number = "12",

}

TY - JOUR

T1 - CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin

AU - Cho, Seong Ik

AU - Heo, Jin Seok

AU - Park, Hong June

AU - Park, Mu Hun

AU - Kim, Young Hee

PY - 2003/12

Y1 - 2003/12

N2 - A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.

AB - A new CMOS sense-amplifier type flip-flop (SAFF) is proposed. By reducing the discharging time and the loading condition, the setup/hold time is improved by 22%, the input data to clock skew by 46% and the clock to output delay by 4.4%.

KW - Flip-flop

KW - Receiver

KW - Sense-amplifier

UR - https://www.scopus.com/pages/publications/0842332051

M3 - Journal article

AN - SCOPUS:0842332051

SN - 0916-8524

VL - E86-C

SP - 2508

EP - 2510

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

IS - 12

ER -

CMOS Sense-Amplifier Type Flip-Flop Having Improved Setup/Hold Margin

Abstract

Keywords

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