Skip to main navigation Skip to search Skip to main content

Code generation for embedded processors with complex instructions

  • Jong Yeol Lee
  • , Hyun Dhong Yoon
  • , Jin Hyuk Yang
  • , In Cheol Park
  • , Chong Min Kyung
  • Korea Advanced Institute of Science and Technology

Research output: Contribution to conference › Conference paper › peer-review

Abstract

Code generation for embedded processors often encounters the problem of using complex instructions. The problems come from the heterogeneous register architecture of the embedded processors, small number of registers, and instructions with complex behaviors. In this paper we propose some techniques for using complex instructions. One of them is a simple technique to use MAC instruction (Modified Pattern Matching). The other two techniques are implemented in the Postpass Optimizer that optimizes the generated code with hardware loop instructions and post-increment or post-decrement addressing modes. Experimental results are also presented.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages525-528
Number of pages4
ISBN (Print)0780357272, 9780780357273
DOIs
StatePublished - 1999
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999.10.26 → 1999.10.27

Publication series

NameICVC 1999 - 6th International Conference on VLSI and CAD

Conference

Conference6th International Conference on VLSI and CAD, ICVC 1999
Country/TerritoryKorea, Republic of
CitySeoul
Period99.10.26 → 99.10.27

Fingerprint

Dive into the research topics of 'Code generation for embedded processors with complex instructions'. Together they form a unique fingerprint.

Cite this