Constant multiplier design using specialized bit pattern adders

Kyung Ju Cho; Suhyun Jo; Yong Eun Kim; Yi Nan Xu; Jin Gyun Chung

doi:10.1109/ICECS.2008.4674786

Constant multiplier design using specialized bit pattern adders

Kyung Ju Cho^*
, Suhyun Jo
, Yong Eun Kim
, Yi Nan Xu
, Jin Gyun Chung

^*Corresponding author for this work

Division of Electronic Engineering

Jeonbuk National University

Research output: Contribution to conference › Conference paper › peer-review

3 Scopus citations

Abstract

The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-2⁴ FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages	41-44
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2008.4674786
State	Published - 2008
Event	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta Duration: 2008.08.31 → 2008.09.3

Publication series

Name	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/Territory	Malta
City	St. Julian's
Period	08.08.31 → 08.09.3

Quacquarelli Symonds(QS) Subject Topics

Engineering - Electrical & Electronic
Engineering - Petroleum

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10.1109/ICECS.2008.4674786

Cite this

Cho, K. J., Jo, S., Kim, Y. E., Xu, Y. N., & Chung, J. G. (2008). Constant multiplier design using specialized bit pattern adders. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 41-44). Article 4674786 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674786

@inproceedings{10d6c529fa5d44b89cf21839d81ac105,

title = "Constant multiplier design using specialized bit pattern adders",

abstract = "The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21\%, 11\% and 12\%, respectively, by the proposed algorithm.",

author = "Cho, \{Kyung Ju\} and Suhyun Jo and Kim, \{Yong Eun\} and Xu, \{Yi Nan\} and Chung, \{Jin Gyun\}",

year = "2008",

doi = "10.1109/ICECS.2008.4674786",

language = "English",

isbn = "9781424421824",

series = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

pages = "41--44",

booktitle = "Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008",

note = "15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 ; Conference date: 31-08-2008 Through 03-09-2008",

}

Cho, KJ, Jo, S, Kim, YE, Xu, YN & Chung, JG 2008, Constant multiplier design using specialized bit pattern adders. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4674786, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pp. 41-44, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 08.08.31. https://doi.org/10.1109/ICECS.2008.4674786

Constant multiplier design using specialized bit pattern adders. / Cho, Kyung Ju; Jo, Suhyun; Kim, Yong Eun et al.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 41-44 4674786 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

Research output: Contribution to conference › Conference paper › peer-review

TY - GEN

T1 - Constant multiplier design using specialized bit pattern adders

AU - Cho, Kyung Ju

AU - Jo, Suhyun

AU - Kim, Yong Eun

AU - Xu, Yi Nan

AU - Chung, Jin Gyun

PY - 2008

Y1 - 2008

N2 - The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.

AB - The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.

UR - https://www.scopus.com/pages/publications/57849108680

U2 - 10.1109/ICECS.2008.4674786

DO - 10.1109/ICECS.2008.4674786

M3 - Conference paper

AN - SCOPUS:57849108680

SN - 9781424421824

T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

SP - 41

EP - 44

BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

T2 - 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Y2 - 31 August 2008 through 3 September 2008

ER -

Cho KJ, Jo S, Kim YE, Xu YN, Chung JG. Constant multiplier design using specialized bit pattern adders. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 41-44. 4674786. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4674786

Constant multiplier design using specialized bit pattern adders

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