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Delay matching compensated CMOS microwave frequency doubler

  • Kyungju Song*
  • , Heungjae Choi
  • , Chul Dong Kim
  • , J. S. Kenney
  • , Yongchae Jeong
  • *Corresponding author for this work
  • Jeonbuk National University
  • Sewon Teletech, Inc.
  • Georgia Institute of Technology

Research output: Contribution to conferenceConference paperpeer-review

Abstract

In this paper, a modified time-delay microwave frequency doubler is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the time-delay mismatching between input and delayed signal. With the delay matching and waveform shaping using adjustable Schmitt triggers, the unwanted fundamental component (f0) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component (2f0) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of f0 and fabricated with TSMC 0.18 μm CMOS process. The measured output power of 2f0 is 2.67 dBm when the input power is 0 dBm. The obtained suppression of f0, 3f0, and 4f0 to 2f 0 are 43.65, 38.65 and 35.59 dB, respectively.

Original languageEnglish
Title of host publicationProceedings of the 38th European Microwave Conference, EuMC 2008
Pages464-467
Number of pages4
DOIs
StatePublished - 2008
Event38th European Microwave Conference, EuMC 2008 - Amsterdam, Netherlands
Duration: 2008.10.272008.10.31

Publication series

NameProceedings of the 38th European Microwave Conference, EuMC 2008

Conference

Conference38th European Microwave Conference, EuMC 2008
Country/TerritoryNetherlands
CityAmsterdam
Period08.10.2708.10.31

Quacquarelli Symonds(QS) Subject Topics

  • Engineering - Electrical & Electronic
  • Engineering - Petroleum

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