Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks

So Hyeon Park; Jae Hee Lee; Hang Geun Jeong; Donggu Im

doi:10.1109/ISOCC50952.2020.9333090

Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks

So Hyeon Park
, Jae Hee Lee
, Hang Geun Jeong
, Donggu Im^*

^*Corresponding author for this work

Division of Electronic Engineering

Jeonbuk National University

Research output: Contribution to conference › Conference paper › peer-review

3 Scopus citations

Abstract

We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 μm CMOS technology. The designed chip occupies a chip area of 408μm × 197μm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	250-251
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333090
State	Published - 2020.10.21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020.10.21 → 2020.10.24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20.10.21 → 20.10.24

Keywords

Analog neuron
CMOS
Squaring circuit
translinear

Quacquarelli Symonds(QS) Subject Topics

Computer Science & Information Systems
Engineering - Electrical & Electronic
Engineering - Petroleum
Data Science
Physics & Astronomy

Access to Document

10.1109/ISOCC50952.2020.9333090

Cite this

Park, S. H., Lee, J. H., Jeong, H. G., & Im, D. (2020). Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 250-251). Article 9333090 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333090

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title = "Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks",

abstract = "We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 μm CMOS technology. The designed chip occupies a chip area of 408μm × 197μm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.",

keywords = "Analog neuron, CMOS, Squaring circuit, translinear",

author = "Park, \{So Hyeon\} and Lee, \{Jae Hee\} and Jeong, \{Hang Geun\} and Donggu Im",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

month = oct,

day = "21",

doi = "10.1109/ISOCC50952.2020.9333090",

language = "English",

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Park, SH, Lee, JH, Jeong, HG & Im, D 2020, Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333090, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 250-251, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20.10.21. https://doi.org/10.1109/ISOCC50952.2020.9333090

Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. / Park, So Hyeon; Lee, Jae Hee; Jeong, Hang Geun et al.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 250-251 9333090 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Contribution to conference › Conference paper › peer-review

TY - GEN

T1 - Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks

AU - Park, So Hyeon

AU - Lee, Jae Hee

AU - Jeong, Hang Geun

AU - Im, Donggu

PY - 2020/10/21

Y1 - 2020/10/21

N2 - We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 μm CMOS technology. The designed chip occupies a chip area of 408μm × 197μm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.

AB - We propose a new current mode CMOS squaring circuit which directly yields the square term. The proposed squaring circuit was designed in a standard with 0.18 μm CMOS technology. The designed chip occupies a chip area of 408μm × 197μm and consumes a power of 3.6mW. The proposed squaring circuit can be used in current mode applications as in analog neurons.

KW - Analog neuron

KW - CMOS

KW - Squaring circuit

KW - translinear

UR - https://www.scopus.com/pages/publications/85100745337

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DO - 10.1109/ISOCC50952.2020.9333090

M3 - Conference paper

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T3 - Proceedings - International SoC Design Conference, ISOCC 2020

SP - 250

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks

Abstract

Publication series

Conference

Keywords

Quacquarelli Symonds(QS) Subject Topics

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