Abstract
In this paper, we propose two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistor 1 and 2 employ a P-type folded composite transistor and an electronic zener. diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25μm n-well process with 2.5V supply voltage.
| Original language | English |
|---|---|
| Pages (from-to) | 1034-1037 |
| Number of pages | 4 |
| Journal | Midwest Symposium on Circuits and Systems |
| Volume | 3 |
| DOIs | |
| State | Published - 2000 |
Quacquarelli Symonds(QS) Subject Topics
- Materials Science
- Engineering - Electrical & Electronic
- Engineering - Petroleum
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