Design of Highly Stackable Charge Trap-Based 3D DRAM

In this work, we propose a highly stackable Charge Trap-based 3D DRAM (CT 3D DRAM) structure that addresses key challenges in future memory scaling, including 3D integration, power consumption, and thermal management. Unlike conventional DRAM architectures that rely on complex capacitor structures, the proposed CT 3D DRAM utilizes a simple 1T memory cell with a poly-Si channel and Schottky barrier source/drain (S/D) contacts formed by metal silicide. Hot carrier injection (HCI) from the source side enables fast program operations through an ultrathin tunnel oxide. Key device parameters were optimized using 3D TCAD simulations, and planar CT DRAM devices were fabricated to validate the concept. The fabricated devices exhibited a program/erase window larger than 1 V under a 20 ns pulse, excellent retention characteristics exceeding 10 seconds at 85° C, and endurance up to 10¹⁵ cycles with a remaining threshold voltage window of approximately 0.32 V. Moreover, the use of metal S/Ds significantly enhances heat dissipation and enables superior thermal management, critical for highly stacked 3D memories. The vertical integration of metal bit lines (BLs) and horizontal poly-Si channels results in lower RC delays, making the CT 3D DRAM scalable even beyond a thousand layers while maintaining effective cell area comparable to conventional 4F² DRAMs. Through the optimized design of the word line (WL) and bit line (BL) structures, as well as control of key materials such as the tunnel oxide and charge trap nitride, we demonstrate that CT 3D DRAM can achieve both high speed and reliability. This architecture offers a promising solution for next-generation 3D DRAM applications requiring high density, low power, and efficient thermal management, particularly in emerging memory platforms like Compute Express Link™ (CXL™) memory.