TY - GEN
T1 - Efficient design of modified Booth multipliers for predetermined coefficients
AU - Kim, Young Eun
AU - Yoon, J. O.
AU - Cho, K. J.
AU - Chung, J. G.
AU - Cho, S. I.
AU - Choi, S. S.
PY - 2006
Y1 - 2006
N2 - Some digital signal processing applications, such as FFT's, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-24 FFT, the area and power consumption can be reduced by 18% and 36%, respectively.
AB - Some digital signal processing applications, such as FFT's, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-24 FFT, the area and power consumption can be reduced by 18% and 36%, respectively.
UR - https://www.scopus.com/pages/publications/34547280229
M3 - Conference paper
AN - SCOPUS:34547280229
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2717
EP - 2720
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -