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Efficient design of multipliers for pre-determined coefficient groups

  • Yong Eun Kim*
  • , Jin Gyun Chung
  • , Myoong Seob Lim
  • *Corresponding author for this work

Research output: Contribution to conferenceConference paperpeer-review

Abstract

Some digital signal processing applications, such as direct digital frequency synthesizer (DDFS), request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on the variation of the CSD coding method, efficient multiplier design method for pre-determined coefficient groups is proposed. In the case of the multiplier of sine-cosine generator used in DDFS, it is shown that by the proposed method, area, power and delay time can be reduced by 53.13%, 45.59% and 22.64%, respectively, compared with conventional design. Also in the case of pulse-shaping filter design used in CDMA, the area, power and delay time can be reduced by 47%, 42.3% and 38%, respectively.

Original languageEnglish
Title of host publicationISSSTA-06 - 2006 IEEE 9th International Symposium on Spread Spectrum Symposium on Spread Spectrum Techniques and Applications, Proceedings
Pages36-40
Number of pages5
DOIs
StatePublished - 2006
EventISSSTA-06 - 2006 IEEE 9th International Symposium on Spread Spectrum Symposium on Spread Spectrum Techniques and Applications - Manaus, Brazil
Duration: 2006.08.282006.08.31

Publication series

NameIEEE International Symposium on Spread Spectrum Techniques and Applications

Conference

ConferenceISSSTA-06 - 2006 IEEE 9th International Symposium on Spread Spectrum Symposium on Spread Spectrum Techniques and Applications
Country/TerritoryBrazil
CityManaus
Period06.08.2806.08.31

Quacquarelli Symonds(QS) Subject Topics

  • Computer Science & Information Systems
  • Engineering - Electrical & Electronic
  • Engineering - Petroleum

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