Efficient ROM size reduction for distributed arithmetic

Jung Pil Choi; Seung Cheol Shin; Jin Gyun Chung

doi:10.1109/ISCAS.2000.856258

Efficient ROM size reduction for distributed arithmetic

Jung Pil Choi^*
, Seung Cheol Shin
, Jin Gyun Chung

^*Corresponding author for this work

Division of Electronic Engineering

Jeonbuk National University

Research output: Contribution to journal › Conference article › peer-review

44 Scopus citations

Abstract

In distributed arithmetic-based architecture for an inner product between two length V vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

Original language	English
Pages (from-to)	II-61-II-64
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2000.856258
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 2000.05.28 → 2000.05.31

Quacquarelli Symonds(QS) Subject Topics

Engineering - Electrical & Electronic
Engineering - Petroleum

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10.1109/ISCAS.2000.856258

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title = "Efficient ROM size reduction for distributed arithmetic",

abstract = "In distributed arithmetic-based architecture for an inner product between two length V vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50\%.",

author = "Choi, \{Jung Pil\} and Shin, \{Seung Cheol\} and Chung, \{Jin Gyun\}",

year = "2000",

doi = "10.1109/ISCAS.2000.856258",

language = "English",

volume = "2",

pages = "II--61--II--64",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

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TY - JOUR

T1 - Efficient ROM size reduction for distributed arithmetic

AU - Choi, Jung Pil

AU - Shin, Seung Cheol

AU - Chung, Jin Gyun

PY - 2000

Y1 - 2000

N2 - In distributed arithmetic-based architecture for an inner product between two length V vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

AB - In distributed arithmetic-based architecture for an inner product between two length V vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their size is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

UR - https://www.scopus.com/pages/publications/0033684180

U2 - 10.1109/ISCAS.2000.856258

DO - 10.1109/ISCAS.2000.856258

M3 - Conference article

AN - SCOPUS:0033684180

SN - 0271-4310

VL - 2

SP - II-61-II-64

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

Efficient ROM size reduction for distributed arithmetic

Abstract

Quacquarelli Symonds(QS) Subject Topics

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