Electrical characteristics of 20-nm junctionless Si nanowire transistors

Chan Hoon Park; Myung Dong Ko; Ki Hyun Kim; Rock Hyun Baek; Chang Woo Sohn; Chang Ki Baek; Sooyoung Park; M. J. Deen; Yoon Ha Jeong; Jeong Soo Lee

doi:10.1016/j.sse.2011.11.032

Electrical characteristics of 20-nm junctionless Si nanowire transistors

Chan Hoon Park
, Myung Dong Ko
, Ki Hyun Kim
, Rock Hyun Baek
, Chang Woo Sohn
, Chang Ki Baek
, Sooyoung Park
, M. J. Deen
, Yoon Ha Jeong
, Jeong Soo Lee^*

^*Corresponding author for this work

Division of Electronic Engineering

Pohang University of Science and Technology
McMaster University
National Center for Nanomaterials Technology (NCNT)

Research output: Contribution to journal › Letter › peer-review

157 Scopus citations

Abstract

We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high I_on/I_off ratio (>10⁶), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.

Original language	English
Pages (from-to)	7-10
Number of pages	4
Journal	Solid-State Electronics
Volume	73
DOIs	https://doi.org/10.1016/j.sse.2011.11.032
State	Published - 2012.07

Keywords

Drain induced barrier lowering
Junctionless transistor
Multigate
Nanowire transistor
Short channel characteristics
Subthreshold slope

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10.1016/j.sse.2011.11.032

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title = "Electrical characteristics of 20-nm junctionless Si nanowire transistors",

abstract = "We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.",

keywords = "Drain induced barrier lowering, Junctionless transistor, Multigate, Nanowire transistor, Short channel characteristics, Subthreshold slope",

author = "Park, \{Chan Hoon\} and Ko, \{Myung Dong\} and Kim, \{Ki Hyun\} and Baek, \{Rock Hyun\} and Sohn, \{Chang Woo\} and Baek, \{Chang Ki\} and Sooyoung Park and Deen, \{M. J.\} and Jeong, \{Yoon Ha\} and Lee, \{Jeong Soo\}",

year = "2012",

month = jul,

doi = "10.1016/j.sse.2011.11.032",

language = "English",

volume = "73",

pages = "7--10",

journal = "Solid-State Electronics",

issn = "0038-1101",

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TY - JOUR

T1 - Electrical characteristics of 20-nm junctionless Si nanowire transistors

AU - Park, Chan Hoon

AU - Ko, Myung Dong

AU - Kim, Ki Hyun

AU - Baek, Rock Hyun

AU - Sohn, Chang Woo

AU - Baek, Chang Ki

AU - Park, Sooyoung

AU - Deen, M. J.

AU - Jeong, Yoon Ha

AU - Lee, Jeong Soo

PY - 2012/7

Y1 - 2012/7

N2 - We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.

AB - We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.

KW - Drain induced barrier lowering

KW - Junctionless transistor

KW - Multigate

KW - Nanowire transistor

KW - Short channel characteristics

KW - Subthreshold slope

UR - https://www.scopus.com/pages/publications/84859374749

U2 - 10.1016/j.sse.2011.11.032

DO - 10.1016/j.sse.2011.11.032

M3 - Letter

AN - SCOPUS:84859374749

SN - 0038-1101

VL - 73

SP - 7

EP - 10

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Electrical characteristics of 20-nm junctionless Si nanowire transistors

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Keywords

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