Abstract
This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.
| Original language | English |
|---|---|
| Pages (from-to) | 1497-1503 |
| Number of pages | 7 |
| Journal | IEICE Transactions on Information and Systems |
| Volume | E93-D |
| Issue number | 6 |
| DOIs | |
| State | Published - 2010.06 |
Keywords
- Digital arithmetic
- Fixed-width
- GCSD multiplier
- Quantization error
Quacquarelli Symonds(QS) Subject Topics
- Computer Science & Information Systems
- Engineering - Electrical & Electronic
- Engineering - Petroleum
- Data Science
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