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High-speed assembly FFT implementation with memory reference reduction on DSP processors

  • Yiyan Tang*
  • , Yuke Wang
  • , Jin Gyun Chung
  • , S. Song
  • , M. Lim
  • *Corresponding author for this work
  • University of Texas at Dallas
  • Jeonbuk National University

Research output: Contribution to conferenceConference paperpeer-review

Abstract

Memory reference in digital signal processors (DSP) is among the most costly operations due to its long latency and substantial power consumption. Previously proposed twiddle-factor-based butterfly grouping method can effectively minimize memory references due to twiddle factors for implementing any existing fast Fourier transform (FFT) algorithms on DSP. However, the performance of its C implementation on DSP is far behind the corresponding TI assembly benchmark for radix-2 DIP FFT due to limitation of the compiler. In this paper, we propose a hand-coded assembly implementation for radix-2 DIP FFT algorithm with twiddle-factor-based butterfly grouping method on TI TMS320C64x DSP. Experimental results show that for 1024-pt radix-2 DIF FFT, our hand-coded assembly implementation is 8 times faster than the C implementation and slightly faster than the TI assembly benchmark while requires only 50% of memory references due to twiddle factors comparing to the TI assembly benchmark.

Original languageEnglish
Title of host publication11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004
Pages547-550
Number of pages4
StatePublished - 2004
Event11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004 - Tel Aviv, Israel
Duration: 2004.12.132004.12.15

Publication series

Name11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004

Conference

Conference11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004
Country/TerritoryIsrael
CityTel Aviv
Period04.12.1304.12.15

Quacquarelli Symonds(QS) Subject Topics

  • Engineering & Technology

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