Hybrid C-V and I-V technique for separate extraction of structure-and bias-dependent parasitic resistances in a-InGaZnO TFTs

We report a hybrid technique for extraction of structure-and gate-bias-dependent parasitic source/drain (S/D) resistances (R _S and R _D) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, C-V and I-V measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness T _IGZO , the gate length L, and the overlap length L _ov between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component R _H considering the transfer resistance R _LT depending on the transfer length L _T and the channel resistance R _CH, as well as the vertical components in the S/D R _VS and R _VD. We confirmed the proposed technique through a separate extraction of V _GS-independent contact resistances (R _CS, R _CD) from the channel length-and V _GS-dependent R _LT and R _CH.