Investigation of low-frequency noise in nonvolatile memory composed of a gate- all-around junctionless nanowire FET

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/ f -shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler-Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO₂)-nitride(SiN_x)-oxide(SiO₂)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state.