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Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor

  • Chang Hoon Jeon
  • , Jun Young Park
  • , Myeong Lok Seol
  • , Dong Il Moon
  • , Jae Hur
  • , Hagyoul Bae
  • , Seung Bae Jeon
  • , Yang Kyu Choi*
  • *Corresponding author for this work
  • Korea Advanced Institute of Science and Technology

Research output: Contribution to journalJournal articlepeer-review

Abstract

Thermal engineering assisted by electrical annealing was applied to enhance the device performance of a gate-all-around (GAA) silicon nanowire (Si-NW) transistor. The ON-state current is increased by four times. Joule heating was produced in a Si-NW by electrical biasing. The heating was concentrated on both edges of the gate, which served as a heat sink, effectively lowering the parasitic external resistance of the GAA Si-NW transistor. The electrical biasing gives rise to a thermal annealing effect on a selected device and to all devices connected by a common biasing electrode. The evidence reported in our previous work regarding current-induced oxidation by Joule heating in a Si-NW was also observed in the measured transfer characteristics of the GAA Si-NW transistor in this paper.

Original languageEnglish
Article number7458209
Pages (from-to)2288-2292
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume63
Issue number6
DOIs
StatePublished - 2016.06

Keywords

  • Gate-all-around (GAA) transistor
  • Joule heating
  • junctionless (JL) MOSFET
  • local annealing
  • silicon nanowire (Si-NW).

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