Low error fixed-width two's complement squarer design using Booth-folding technique

This study presents a design method for fixed-width two's complement squarer that receives an n-bit input and produces an n-bit squared product. To efficiently compensate for the truncation error, modified Booth-folding encoder signals are used for the generation of error compensation bias. The truncated bits are divided into two groups depending on their effects on the truncation error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the true rounding method and much better than those of other methods. Also, it is shown that the proposed fixed-width two's complement squarers lead to about 34 reduction in area, 35 reduction in power consumption and 10 improvement in speed compared with conventional squarers.