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Low Latency IFFT Design for 3GPP LTE

  • Jeonbuk National University
  • Electronics and Telecommunications Research Institute
  • Wonkwang University

Research output: Contribution to conferenceConference paperpeer-review

Abstract

In this paper, a low latency IFFT architecture for Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed architecture was verified using Altera Modelsim.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages69-70
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 2016.12.27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016.10.232016.10.26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Conference

Conference13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of
CityJeju
Period16.10.2316.10.26

Keywords

  • IFFT
  • Latency reduction
  • Memory size
  • Null signal

Quacquarelli Symonds(QS) Subject Topics

  • Computer Science & Information Systems
  • Engineering - Electrical & Electronic
  • Engineering - Petroleum
  • Physics & Astronomy

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