TY - GEN
T1 - Low-power FFT design for NC-OFDM in cognitive radio systems
AU - Jang, In Gul
AU - Piao, Zhe Yan
AU - Dong, Ze Hua
AU - Chung, Jin Gyun
AU - Lee, Kang Yoon
PY - 2011
Y1 - 2011
N2 - Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as 0. In this paper, based on the fact that there are many 0 input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24 SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.
AB - Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as 0. In this paper, based on the fact that there are many 0 input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24 SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.
UR - https://www.scopus.com/pages/publications/79960850246
U2 - 10.1109/ISCAS.2011.5938099
DO - 10.1109/ISCAS.2011.5938099
M3 - Conference paper
AN - SCOPUS:79960850246
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2449
EP - 2452
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -