TY - GEN
T1 - Memory reduction of IFFT using CIM(combined integer mapping) for OFDM transmitters
AU - Seo, Dong Hyun
AU - Jang, In Gul
AU - Chung, Jin Gyun
AU - Lee, Chul Dong
PY - 2010
Y1 - 2010
N2 - FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically (log2N) as the transform length (N) increases, the number of required registers (or, memories) increases linearly. In large transform length FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined integer mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 34.7% area reduction and 33.4% power reduction compared with conventional IFFT designs.
AB - FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically (log2N) as the transform length (N) increases, the number of required registers (or, memories) increases linearly. In large transform length FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined integer mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 34.7% area reduction and 33.4% power reduction compared with conventional IFFT designs.
UR - https://www.scopus.com/pages/publications/77957274248
U2 - 10.1109/SIBIRCON.2010.5555186
DO - 10.1109/SIBIRCON.2010.5555186
M3 - Conference paper
AN - SCOPUS:77957274248
SN - 9781424476268
T3 - Proceedings - 2010 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON-2010
SP - 268
EP - 273
BT - Proceedings - 2010 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON-2010
T2 - 2010 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON-2010
Y2 - 11 July 2010 through 15 July 2010
ER -