Modeling and separate extraction technique for gate bias-dependent parasitic resistances and overlap length in MOSFETs

Jungmin Lee; Hagyoul Bae; Jun Seok Hwang; Jaeyeop Ahn; Jun Tae Jang; Jinsoo Yoon; Sung Jin Choi; Dae Hwan Kim; Dong Myong Kim

doi:10.1109/TED.2015.2388704

Modeling and separate extraction technique for gate bias-dependent parasitic resistances and overlap length in MOSFETs

Jungmin Lee
, Hagyoul Bae
, Jun Seok Hwang
, Jaeyeop Ahn
, Jun Tae Jang
, Jinsoo Yoon
, Sung Jin Choi
, Dae Hwan Kim
, Dong Myong Kim

Division of Electronic Engineering

Kookmin University

Research output: Contribution to journal › Journal article › peer-review

10 Scopus citations

Abstract

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (R_Se/R_De) and gate bias (V_GS)-dependent but channel length (L)-independent intrinsic source/drain (R_Si/R_Di) resistances for the overlap region in MOSFETs. For extraction of the overlap length (L_ov)in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (C_G-S , C_G-D) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract V_GS-dependent R_Si= 0.9 ∼ 3.7~Ω and R_Di= 1.0 ∼ 3.9~ Ω in an n-channel MOSFET with W=140~ μ m and L=0.35 ~μ m. In addition, V_GS-and L-independent extrinsic S/D resistances are separately extracted to be R_Se=5.1~ Ω and R_De= 5.0~Ω , respectively.

Original language	English
Article number	7014227
Pages (from-to)	1063-1067
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	62
Issue number	3
DOIs	https://doi.org/10.1109/TED.2015.2388704
State	Published - 2015.03

Keywords

Drain resistance
extrinsic resistance
intrinsic
MOSFET
overlap length (Lov)
Source resistance

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10.1109/TED.2015.2388704

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@article{1db09b8c67cc416798d3f969c4ebe930,

title = "Modeling and separate extraction technique for gate bias-dependent parasitic resistances and overlap length in MOSFETs",

abstract = "We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (RSe/RDe) and gate bias (VGS)-dependent but channel length (L)-independent intrinsic source/drain (RSi/RDi) resistances for the overlap region in MOSFETs. For extraction of the overlap length (Lov)in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (CG-S , CG-D) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract VGS-dependent RSi= 0.9 ∼ 3.7\textasciitilde{}Ω and RDi= 1.0 ∼ 3.9\textasciitilde{} Ω in an n-channel MOSFET with W=140\textasciitilde{} μ m and L=0.35 \textasciitilde{}μ m. In addition, VGS-and L-independent extrinsic S/D resistances are separately extracted to be RSe=5.1\textasciitilde{} Ω and RDe= 5.0\textasciitilde{}Ω , respectively.",

keywords = "Drain resistance, extrinsic resistance, intrinsic, MOSFET, overlap length (Lov), Source resistance",

author = "Jungmin Lee and Hagyoul Bae and Hwang, \{Jun Seok\} and Jaeyeop Ahn and Jang, \{Jun Tae\} and Jinsoo Yoon and Choi, \{Sung Jin\} and Kim, \{Dae Hwan\} and Kim, \{Dong Myong\}",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2015",

month = mar,

doi = "10.1109/TED.2015.2388704",

language = "English",

volume = "62",

pages = "1063--1067",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

number = "3",

}

TY - JOUR

T1 - Modeling and separate extraction technique for gate bias-dependent parasitic resistances and overlap length in MOSFETs

AU - Lee, Jungmin

AU - Bae, Hagyoul

AU - Hwang, Jun Seok

AU - Ahn, Jaeyeop

AU - Jang, Jun Tae

AU - Yoon, Jinsoo

AU - Choi, Sung Jin

AU - Kim, Dae Hwan

AU - Kim, Dong Myong

PY - 2015/3

Y1 - 2015/3

N2 - We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (RSe/RDe) and gate bias (VGS)-dependent but channel length (L)-independent intrinsic source/drain (RSi/RDi) resistances for the overlap region in MOSFETs. For extraction of the overlap length (Lov)in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (CG-S , CG-D) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract VGS-dependent RSi= 0.9 ∼ 3.7~Ω and RDi= 1.0 ∼ 3.9~ Ω in an n-channel MOSFET with W=140~ μ m and L=0.35 ~μ m. In addition, VGS-and L-independent extrinsic S/D resistances are separately extracted to be RSe=5.1~ Ω and RDe= 5.0~Ω , respectively.

AB - We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (RSe/RDe) and gate bias (VGS)-dependent but channel length (L)-independent intrinsic source/drain (RSi/RDi) resistances for the overlap region in MOSFETs. For extraction of the overlap length (Lov)in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (CG-S , CG-D) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract VGS-dependent RSi= 0.9 ∼ 3.7~Ω and RDi= 1.0 ∼ 3.9~ Ω in an n-channel MOSFET with W=140~ μ m and L=0.35 ~μ m. In addition, VGS-and L-independent extrinsic S/D resistances are separately extracted to be RSe=5.1~ Ω and RDe= 5.0~Ω , respectively.

KW - Drain resistance

KW - extrinsic resistance

KW - intrinsic

KW - MOSFET

KW - overlap length (Lov)

KW - Source resistance

UR - https://www.scopus.com/pages/publications/85027958155

U2 - 10.1109/TED.2015.2388704

DO - 10.1109/TED.2015.2388704

M3 - Journal article

AN - SCOPUS:85027958155

SN - 0018-9383

VL - 62

SP - 1063

EP - 1067

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

M1 - 7014227

ER -

Modeling and separate extraction technique for gate bias-dependent parasitic resistances and overlap length in MOSFETs

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