Abstract
We fabricated the Au/n-type Ge Schottky barrier diodes (SBDs) by introducing a graphene interlayer in-between Au and n-type Ge. Then we investigated the effects of the graphene interlayer on their electrical properties using the current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Schottky barrier properties of Au/n-type Ge SBDs with and without graphene interlayer were cross-checked by various analysis techniques such as forward I-V, C-V, Cheung's, and Norde's methods. The Au/n-type Ge SBD with graphene interlayer exhibited lower ideality factor and series resistance, as compared to Au/n-type Ge SBD. The barrier height of Au/graphene/n-type Ge SBD was higher than that of Au/n-type Ge SBD. It is observed that the Fermi-level pinning at Au/Ge Schottky junction was released by the graphene interlayer. The Fermi-level depinning behavior of Ge was also observed in the graphene-interlayered Ti contact to n-type Ge. The introduction of the graphene interlayer to Au/n-type Ge SBD led to a significant reduction of interface state density (Nss) associated with the passivation of Ge surface by graphene, which could be responsible for minimizing the Fermi-level pinning of Ge.
| Original language | English |
|---|---|
| Pages (from-to) | 323-329 |
| Number of pages | 7 |
| Journal | Journal of Alloys and Compounds |
| Volume | 614 |
| DOIs | |
| State | Published - 2014.11.25 |
Keywords
- Fermi-level depinning
- Graphene interlayer
- n-Type Ge
- Schottky barrier diode
Quacquarelli Symonds(QS) Subject Topics
- Engineering - Mechanical
- Materials Science
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