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Modified CSD group multiplier design for predetermined coeffecient groups

  • Yong Eun Kim*
  • , Su Hyun Cho
  • , Jin Gyun Chung
  • *Corresponding author for this work
  • Jeonbuk National University

Research output: Contribution to conferenceConference paperpeer-review

Abstract

Some digital signal processing applications, such as FFT, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on a grouping method of CSD coefficients, an efficient multiplier design method for predetermined coefficient groups is proposed. In the case of the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), it is shown that by the proposed method, area, power and delay time can be reduced by 53.1%, 45.6% and 22.6%, respectively, compared with conventional design. Also, in the case of multiplier design used in 128 point radix-24 FFT, the area, power and delay time can be reduced by 42.9%, 58.5% and 19.7%, respectively.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages3362-3365
Number of pages4
DOIs
StatePublished - 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 2008.05.182008.05.21

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/TerritoryUnited States
CitySeattle, WA
Period08.05.1808.05.21

Quacquarelli Symonds(QS) Subject Topics

  • Engineering - Electrical & Electronic
  • Engineering - Petroleum

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