New design of spotty and adjacent symbol error correction codes for high-speed interconnects

During data transmission by high-speed interconnect and memory devices, errors with patterns known to have spotty and adjacent characteristics can occur. To ensure fast and reliable computing systems, an efficient design of error correcting codes (ECCs) for the spotty and adjacent symbol errors (SASEs) is necessary. In this paper, we propose a new class of spotty and adjacent symbol error correction (SASEC) codes for the first time. Interestingly, the proposed SASEC codes are devised using the extended coset basis codes and interleaved Bose-Chaudhuri-Hocquenghem (BCH) codes. The proposed SASEC codes are highlighted by the advantages of their enhanced error correction capability and lower parity overhead compared to the existing single error correction and double error detection (SECDED) codes and symbol error correcting Reed-Solomon (RS) codes, respectively. In addition, low-complexity syndrome decoding (LCSD) for the proposed SASEC codes is proposed. High-level synthesis (HLS) results on a field-programmable gate array (FPGA) show that the proposed LCSD can be implemented with low decoding overhead comparable to that of the ROM-table-based decoder for the SECDED codes.