Novel logic device for CMOS standard I/O cell with tolerance to total ionizing dose effects

This paper deals with a radiation hardening technology for the logic in a commercial CMOS bulk process and the possibility to develop a radiation-hardened (RH) logic standard cell to design RH-integrated circuits (ICs) for a total ionizing dose (TID) environment. We designed a RH logic structure that can be used in a standard I/O cell form by expanding/modifying the RH I-gate n-MOSFET, which was complemented with the IC design complexity of conventional RH n-MOSFETs with a layout modification technique. The radiation-tolerance characteristics of the RH inverter, NAND and NOR were predicted and verified using the radiation effects 3D modeling and simulation (M&S) technique. The RH logic chip was fabricated in SKhynix/Magnachip 0.18 um CMOS process. The test evaluation of the TID effects on the chip was conducted using Cobalt 60 Gamma-ray of 10 kGy(Si)/h for 2 h. As a result, up to total dose of 20 kGy(Si), a radiation damage of the regular logic and a radiation tolerance characteristics of the proposed logic were confirmed. These results will contribute greatly to the design of ICs for nuclear power plants as well as for military and space applications.