Partial-Chip Extensions of Single-Chip Erasure Decoding for Flexible Use of Redundancy

As DRAM density scales, multi-bit and burst errors increasingly threaten system reliability. Prior work introduced single-chip erasure decoding using Reed-Solomon (RS) codes, but it was limited to full-chip erasure and lacked quantitative failure analysis. In this paper, we extend this approach to partial-chip erasure, where only a subset of symbols within a chip is treated as erasures. Using RS(40,32), our simulations show that partial-chip erasure reduces decoding failure probability by up to 70% compared to the full-chip method. We further propose a chip-localized post-decoding filter to eliminate miscorrections and a parallel decoding framework that applies the scheme selectively to high-weight error patterns. Together, these methods lower failure probability and improve design flexibility under the same redundancy budget.