TY - GEN
T1 - Power and area efficient squarer design
AU - Cho, Kyung Ju
AU - Kim, Yong Eun
AU - Chung, Jin Gyun
PY - 2006
Y1 - 2006
N2 - The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present a high performance parallel squarer design method. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.
AB - The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present a high performance parallel squarer design method. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.
UR - https://www.scopus.com/pages/publications/47049118716
U2 - 10.1109/ACSSC.2006.355055
DO - 10.1109/ACSSC.2006.355055
M3 - Conference paper
AN - SCOPUS:47049118716
SN - 1424407850
SN - 9781424407859
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1721
EP - 1725
BT - Conference Record of the 40th Asilomar Conference on Signals, Systems and Computers, ACSSC '06
PB - IEEE Computer Society
T2 - 40th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2006
Y2 - 29 October 2006 through 1 November 2006
ER -