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PWM Switching Pattern for Reducing Voltage Spike on Common-Mode Voltage in Three-Phase Inverters

  • Jeonbuk National University
  • Pusan National University

Research output: Contribution to conferenceConference paperpeer-review

Abstract

This paper suggests a pulse width modulation (PWM) switching pattern to reduce voltage spikes in the common-mode voltage (CMV) of three-phase inverters. These spikes are mainly caused by fast switching and the effects of parasitic capacitances, which can lead to problems like electromagnetic interference (EMI) and early bearing damage. Although existing reduced CMV-PWM (RCMV-PWM) methods help lower CMV, they still suffer from sudden spikes that reduce their overall effect. To solve this, we study the cause of the spikes in active zero state PWM (AZSPWM) and create a better switching pattern. The new method helps reduce CMV spikes in all motor operating conditions. Its performance is confirmed through both simulation, showing better results than conventional SVPWM and AZSPWM.

Original languageEnglish
Title of host publication2025 IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798331541309
DOIs
StatePublished - 2025
Event17th Annual IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025 - Philadelphia, United States
Duration: 2025.10.192025.10.23

Publication series

Name2025 IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025

Conference

Conference17th Annual IEEE Energy Conversion Conference Congress and Exposition, ECCE 2025
Country/TerritoryUnited States
CityPhiladelphia
Period25.10.1925.10.23

Keywords

  • common mode voltage
  • pulse width modulation
  • switching pattern
  • voltage spike

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