Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC I-V Characterization

Do Hyun Kim; Sung Kwan Lim; Hagyoul Bae; Choong Ki Kim; Seung Wook Lee; Myungsoo Seo; Seong Yeon Kim; Kyu Man Hwang; Geon Beom Lee; Byoung Hun Lee; Yang Kyu Choi

doi:10.1109/TED.2018.2805316

Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC I-V Characterization

Do Hyun Kim
, Sung Kwan Lim
, Hagyoul Bae
, Choong Ki Kim
, Seung Wook Lee
, Myungsoo Seo
, Seong Yeon Kim
, Kyu Man Hwang
, Geon Beom Lee
, Byoung Hun Lee
, Yang Kyu Choi^*

^*Corresponding author for this work

Division of Electronic Engineering

Korea Advanced Institute of Science and Technology
SK Corporation
Gwangju Institute of Science and Technology
Samsung

Research output: Contribution to journal › Journal article › peer-review

18 Scopus citations

Abstract

Deuterium (D₂) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (μ) was extracted using the gate transconductance (gm) method. It was found that μ was improved before and after D₂ annealing. The interface trap density (D_it) as well as the oxide trap density (N_ot) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of N_ot along the depth direction was investigated before and after D₂ annealing using LFN characteristics. It was confirmed that D_it as well as N_ot was reduced by the D₂ annealing, resulting in a reduction in power spectral density and variation.

Original language	English
Pages (from-to)	1640-1644
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	4
DOIs	https://doi.org/10.1109/TED.2018.2805316
State	Published - 2018.04

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@article{e218939503bd4af7abeb5008698726e9,

title = "Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC I-V Characterization",

abstract = "Deuterium (D2) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (μ) was extracted using the gate transconductance (gm) method. It was found that μ was improved before and after D2 annealing. The interface trap density (Dit) as well as the oxide trap density (Not) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of Not along the depth direction was investigated before and after D2 annealing using LFN characteristics. It was confirmed that Dit as well as Not was reduced by the D2 annealing, resulting in a reduction in power spectral density and variation.",

author = "Kim, \{Do Hyun\} and Lim, \{Sung Kwan\} and Hagyoul Bae and Kim, \{Choong Ki\} and Lee, \{Seung Wook\} and Myungsoo Seo and Kim, \{Seong Yeon\} and Hwang, \{Kyu Man\} and Lee, \{Geon Beom\} and Lee, \{Byoung Hun\} and Choi, \{Yang Kyu\}",

note = "Publisher Copyright: {\textcopyright} 2012 IEEE.",

year = "2018",

month = apr,

doi = "10.1109/TED.2018.2805316",

language = "English",

volume = "65",

pages = "1640--1644",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

number = "4",

}

TY - JOUR

T1 - Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC I-V Characterization

AU - Kim, Do Hyun

AU - Lim, Sung Kwan

AU - Bae, Hagyoul

AU - Kim, Choong Ki

AU - Lee, Seung Wook

AU - Seo, Myungsoo

AU - Kim, Seong Yeon

AU - Hwang, Kyu Man

AU - Lee, Geon Beom

AU - Lee, Byoung Hun

AU - Choi, Yang Kyu

PY - 2018/4

Y1 - 2018/4

N2 - Deuterium (D2) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (μ) was extracted using the gate transconductance (gm) method. It was found that μ was improved before and after D2 annealing. The interface trap density (Dit) as well as the oxide trap density (Not) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of Not along the depth direction was investigated before and after D2 annealing using LFN characteristics. It was confirmed that Dit as well as Not was reduced by the D2 annealing, resulting in a reduction in power spectral density and variation.

AB - Deuterium (D2) annealing was applied to a poly-crystalline silicon thin-film transistor (poly-Si TFT) to improve reliability and performance. The field-effect electron mobility (μ) was extracted using the gate transconductance (gm) method. It was found that μ was improved before and after D2 annealing. The interface trap density (Dit) as well as the oxide trap density (Not) in the poly-Si TFTs was quantitatively extracted using both conventional dc I-V characterization and analysis of low frequency noise (LFN). The profile of Not along the depth direction was investigated before and after D2 annealing using LFN characteristics. It was confirmed that Dit as well as Not was reduced by the D2 annealing, resulting in a reduction in power spectral density and variation.

UR - https://www.scopus.com/pages/publications/85042848246

U2 - 10.1109/TED.2018.2805316

DO - 10.1109/TED.2018.2805316

M3 - Journal article

AN - SCOPUS:85042848246

SN - 0018-9383

VL - 65

SP - 1640

EP - 1644

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 4

ER -

Quantitative Analysis of Deuterium Annealing Effect on Poly-Si TFTs by Low Frequency Noise and DC I-V Characterization

Abstract

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