SOI CMOS miniaturized tunable bandpass filter with two transmission zeros for high power applications

This paper presents a capacitor loaded tunable bandpass chip filter using planar multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. This saves chip area by removing an additional resonator for transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The digitally programmable 1 bit capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5 GHz. The proposed on-chip filter is implemented in 0.18-1m SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only 4mm×2mm (i.e., 0:177λg×0:088λg), where λg denotes the guided wave length of the 50Ωmicrostrip line at center frequency. The measured insertion loss (S ₂₁) is about 5.1 dB and 6.9 dB at 5.4 GHz and 4.5 GHz, respectively. The designed filter shows out-of-band rejection greater than 20 dB at 500MHz offset from center frequency.