Vertically integrated ZRAM toward extremely scaled memory

B. H. Lee; D. C. Ahn; M. H. Kang; S. B. Jeon; T. Bang; H. Bae; J. Y. Park; D. W. Hong; N. S. Park; Y. K. Choi

doi:10.1149/07505.0311ecst

Vertically integrated ZRAM toward extremely scaled memory

B. H. Lee
, D. C. Ahn
, M. H. Kang
, S. B. Jeon
, T. Bang
, H. Bae
, J. Y. Park
, D. W. Hong
, N. S. Park
, Y. K. Choi

Division of Electronic Engineering

Korea Advanced Institute of Science and Technology
Samsung
National NanoFab Center

Research output: Contribution to conference › Conference paper › peer-review

Abstract

This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.

Original language	English
Title of host publication	Semiconductors, Dielectrics, and Metals for Nanoelectronics 14
Editors	S. Kar, K. Kita, D. Landheer, D. Misra
Publisher	Electrochemical Society Inc.
Pages	311-316
Number of pages	6
Edition	5
ISBN (Electronic)	9781607687221, 9781607687672, 9781607687689, 9781607687696, 9781607687702, 9781607687719, 9781607687726, 9781607687733, 9781607687740, 9781607687757, 9781607687771, 9781607687788, 9781607687795, 9781607687801, 9781607687818, 9781607687825, 9781607687832, 9781607687849, 9781607687856, 9781607687863, 9781607687887, 9781607687894, 9781607687900, 9781607687917, 9781607687924, 9781607687931, 9781607687948, 9781607687955, 9781607687962, 9781607687979, 9781607687986, 9781607687993, 9781607688006, 9781607688013, 9781607688020, 9781607688037
DOIs	https://doi.org/10.1149/07505.0311ecst
State	Published - 2016
Event	Symposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 - PRiME 2016/230th ECS Meeting - Honolulu, United States Duration: 2016.10.2 → 2016.10.7

Publication series

Name	ECS Transactions
Number	5
Volume	75
ISSN (Print)	1938-6737
ISSN (Electronic)	1938-5862

Conference

Conference	Symposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 - PRiME 2016/230th ECS Meeting
Country/Territory	United States
City	Honolulu
Period	16.10.2 → 16.10.7

Access to Document

10.1149/07505.0311ecst

Cite this

Lee, B. H., Ahn, D. C., Kang, M. H., Jeon, S. B., Bang, T., Bae, H., Park, J. Y., Hong, D. W., Park, N. S., & Choi, Y. K. (2016). Vertically integrated ZRAM toward extremely scaled memory. In S. Kar, K. Kita, D. Landheer, & D. Misra (Eds.), Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 (5 ed., pp. 311-316). (ECS Transactions; Vol. 75, No. 5). Electrochemical Society Inc.. https://doi.org/10.1149/07505.0311ecst

@inproceedings{cdcc5944eaf8450b94890b05622672f5,

title = "Vertically integrated ZRAM toward extremely scaled memory",

abstract = "This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.",

author = "Lee, \{B. H.\} and Ahn, \{D. C.\} and Kang, \{M. H.\} and Jeon, \{S. B.\} and T. Bang and H. Bae and Park, \{J. Y.\} and Hong, \{D. W.\} and Park, \{N. S.\} and Choi, \{Y. K.\}",

note = "Publisher Copyright: {\textcopyright} 2016 The Electrochemical Society.; Symposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 - PRiME 2016/230th ECS Meeting ; Conference date: 02-10-2016 Through 07-10-2016",

year = "2016",

doi = "10.1149/07505.0311ecst",

language = "English",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "5",

pages = "311--316",

editor = "S. Kar and K. Kita and D. Landheer and D. Misra",

booktitle = "Semiconductors, Dielectrics, and Metals for Nanoelectronics 14",

edition = "5",

}

Lee, BH, Ahn, DC, Kang, MH, Jeon, SB, Bang, T, Bae, H, Park, JY, Hong, DW, Park, NS & Choi, YK 2016, Vertically integrated ZRAM toward extremely scaled memory. in S Kar, K Kita, D Landheer & D Misra (eds), Semiconductors, Dielectrics, and Metals for Nanoelectronics 14. 5 edn, ECS Transactions, no. 5, vol. 75, Electrochemical Society Inc., pp. 311-316, Symposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 - PRiME 2016/230th ECS Meeting, Honolulu, United States, 16.10.2. https://doi.org/10.1149/07505.0311ecst

Vertically integrated ZRAM toward extremely scaled memory. / Lee, B. H.; Ahn, D. C.; Kang, M. H. et al.
Semiconductors, Dielectrics, and Metals for Nanoelectronics 14. ed. / S. Kar; K. Kita; D. Landheer; D. Misra. 5. ed. Electrochemical Society Inc., 2016. p. 311-316 (ECS Transactions; Vol. 75, No. 5).

Research output: Contribution to conference › Conference paper › peer-review

TY - GEN

T1 - Vertically integrated ZRAM toward extremely scaled memory

AU - Lee, B. H.

AU - Ahn, D. C.

AU - Kang, M. H.

AU - Jeon, S. B.

AU - Bang, T.

AU - Bae, H.

AU - Park, J. Y.

AU - Hong, D. W.

AU - Park, N. S.

AU - Choi, Y. K.

PY - 2016

Y1 - 2016

N2 - This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.

AB - This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.

UR - https://www.scopus.com/pages/publications/84991449421

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DO - 10.1149/07505.0311ecst

M3 - Conference paper

AN - SCOPUS:84991449421

T3 - ECS Transactions

SP - 311

EP - 316

BT - Semiconductors, Dielectrics, and Metals for Nanoelectronics 14

A2 - Kar, S.

A2 - Kita, K.

A2 - Landheer, D.

A2 - Misra, D.

PB - Electrochemical Society Inc.

T2 - Symposium on Semiconductors, Dielectrics, and Metals for Nanoelectronics 14 - PRiME 2016/230th ECS Meeting

Y2 - 2 October 2016 through 7 October 2016

ER -

Vertically integrated ZRAM toward extremely scaled memory

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